Instructions Scheduling for Highly Super-scalar Processors

Super-scalar processors can execute multiple instructions out-of-order per cycle and speculatively execute instructions through branches. Such processors invalidate many of the assumptions of traditional instruction scheduling. This article analyzes the impact of super-scalar processor architecture upon instruction scheduling. The compile-time schedule is shown to signiicantly impact performance, despite out-of-order execution. The problem of determining an optimal schedule at compile-time is shown to be NP-complete. A variety of heuristics for instructions scheduling are applied to benchmarks, and it is shown that traditional depth-rst instruction scheduling performs badly compared to a variety of breadth-rst instruction scheduling heuristics. Modern high-performance microprocessors, such as the HP PA-8000012] or the PowerPC 62004], are all super-scalar, meaning that they can simultaneously fetch, decode, and execute several instructions at once. Current processors are often at least 4-way super-scalar. Together with the ability to execute multiple instructions in a single cycle, such highly super-scalar processors usually have several other characteristics that signiicantly impact compiler optimization and instruction scheduling, including: Run-time Instruction Scheduling After instructions have been fetched and decoded, they are placed in an instruction reorder buuer awaiting execution. Instructions are executed out-of-order, meaning that an instruction in the instruction buuer is scheduled for execution when all of its operands are available. Run-time Register Renaming Most instruction sets are limited to about 32 real registers. Reuse of registers thus creates anti-dependences: a write into a register can connict with a preceding read. Register renaming eliminates such dependencies by internally mapping instruction set registers to a larger set of virtual registers. Each time a register is written, it is dynamically assigned a new virtual register, thus converting the program dynamically into a single-assignment form. Speculative Execution The direction of conditional branches can be predicted at run-time, using a cache of previous branch directions. If the outcome of a conditional branch prediction is incorrect, all instructions subsequent to the branch are re-executed. Modern processors can speculatively predict through many branches and recover from an incorrect prediction in a single cycle. between register accesses when instructions are decoded. However, dependences between memory access may not be known until the eeective address of the LOAD and STORE instructions are calculated at run-time. This would seem to imply that LOAD and STORE instructions must be executed in order. However, LOADs and STOREs can speculatively execute out of order, provided that such instructions are committed to memory in order, and runtime dependences are detected …